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16-bit, 1 msps/500 ksps differential pulsar adcs data sheet ad7915 / ad7916 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features low power dissipation ad7915 4 mw at 1 msps (vdd only) 7 mw at 1 msps (total) ad7916 2 mw at 500 ksps (vdd only) 3.7 mw at 500 ksps (total) 16-bit resolution with no missing codes throughput: 1 msps ( ad7915 )/500 ksps ( ad7916 ) inl: 0.4 lsb typical, 1 lsb maximum snr: 94 db at 1 khz, v ref = 5 v sinad: 93.5 db at 1 khz, v ref = 5 v thd: ?118.5 db at 1 khz dynamic range: 95.5 db, v ref = 5 v true differential analog input range: v ref 0 v to v ref with v ref between 2.4 v and 5.1 v no pipeline delay single-supply 2.5 v operation wi th 1.8 v/2.5 v/3 v/5 v logic interface proprietary serial interface: spi-/qspi-/microwire?-/dsp- compatible 1 ability to daisy-chain multiple adcs 10-lead packages: msop and 3 mm 3 mm lfcsp applications battery-powered equipment data acquisition systems medical instruments seismic data acquisition systems general description the ad7915 / ad7916 are 16-bit, successive approximation, analog-to-digital converters (adcs) that operate from a single power supply, vdd. they contain a low power, high speed, 16-bit sampling adc and a versatile serial interface port. on the cnv rising edge, the ad7915 / ad7916 sample the voltage difference between the in+ and in? pins. the voltages on these pins typically swing in opposite phases between 0 v and v ref . the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. the power consumption of the ad7915 / ad7916 scales linearly with throughput. the ad7915 / ad7916 are serial peripheral interface (spi) compatible, which features the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus. they are compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic using the separate vio supply. the ad7915/ ad7916 are available in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +125c. table 1. msop, lfcsp 14-/16-/18-bit pulsar? adcs bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps 18 1 ad7989-1 2 ad7691 2 ad7690 2 ad7982 2 ad7989-5 2 ad7984 2 16 1 ad7684 ad7687 2 ad7688 2 ad7915 2 ad7693 2 ad7916 2 16 3 ad7680 ad7685 2 ad7686 2 ad7980 2 ad7683 ad7694 ad7988-5 2 ad7983 2 ad7988-1 2 14 3 ad7940 ad7942 2 ad7946 2 1 true differential. 2 pin-for-pin compatible. 3 pseudo differential. typical applications circuit ref gnd vdd in+ in? vio sdi/cs sck sdo cnv 1.8v to 5.5v ada4940-1 3- or 4-wire interface (spi, cs, daisy chain) 2.5v to 5 v 2.5 v 10v, 5v, .. ad7915/ ad7916 12583-001 figure 1. 1 protected by u.s. patent 6,703,961.
ad7915/ad7916 data sheet rev. 0 | page 2 of 26 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical applications circuit ............................................................ 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 12 ? theory of operation ...................................................................... 13 ? circuit information .................................................................... 13 ? converter operation .................................................................. 13 ? typical connecti on diagram ................................................... 14 ? analog inputs .............................................................................. 15 ? driver amplifier choice ............................................................ 15 ? single to differential driver ..................................................... 16 ? voltage reference input ............................................................ 16 ? power supply ............................................................................... 16 ? digital interface .......................................................................... 16 ? cs mode, 3-wire, without busy indicator ............................ 17 ? cs mode 3-wire, with busy indicator .................................... 18 ? cs mode, 4-wire, without busy indicator ............................ 19 ? cs mode 4-wire with busy indicator ..................................... 20 ? chain mode, without busy indicator ..................................... 21 ? chain mode with busy indicator ............................................. 22 ? applications information .............................................................. 23 ? interfacing to blackfin dsp ...................................................... 23 ? layout .......................................................................................... 23 ? evaluating ad7915/ad7916 performance ............................ 24 ? outline dimensions ....................................................................... 25 ? ordering guide .......................................................................... 25 ? revision history 3/15revision 0: initial version
data sheet ad7915/ad7916 rev. 0 | page 3 of 26 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = ?40c to +125c, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit resolution 16 bits analog input voltage range in+ ? in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? v ref 0.475 v ref 0.5 v ref 0.525 v analog input common-mode rejection ratio (cmrr) f in = 450 khz 60 db leakage current at 25c acquisition phase 1 na input impedance see the analog inputs section accuracy no missing codes 16 bits differential nonlinearity (dnl) error v ref = 5 v ?0.9 0.4 +0.9 lsb 1 v ref = 2.5 v 0.5 lsb 1 integral nonlinearity (inl) error v ref = 5 v ?1 0.4 +1 lsb 1 v ref = 2.5 v 0.5 lsb 1 transition noise v ref = 5 v 0.75 lsb 1 v ref = 2.5 v 1.2 lsb 1 gain error 2 t min to t max ?10 0 +10 lsb 1 gain error temperature drift 0.23 ppm/c zero error 2 t min to t max ?0.5 0.08 +0.5 mv zero temperature drift 0.28 ppm/c power supply sensitivity vdd = 2.5 v 5% 0.1 db throughput ad7915 conversion rate 0 1000 ksps ad7916 conversion rate 0 500 ksps transient response full-scale step 290 ns ac accuracy dynamic range v ref = 5 v 95.5 db 3 v ref = 2.5 v 92 db 3 oversampled dynamic range 4 f o = 10 ksps 113.5 db 3 signal-to-noise ratio (snr) f in = 1 khz, v ref = 5 v 93 94 db 3 f in = 1 khz, v ref = 2.5 v 89 91 db 3 spurious-free dynamic range (sfdr) f in = 1 khz ?118 db 3 total harmonic distortion (thd) f in = 1 khz ?118.5 db 3 signal-to-noise-and-distortion ratio (sinad) f in = 1 khz, v ref = 5 v 93.5 db 3 f in = 1 khz, v ref = 2.5 v 90.5 db 3 reference voltage range 2.4 5.1 v load current v ref = 5 v 330 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2 ns
ad7915/ad7916 data sheet rev. 0 | page 4 of 26 parameter test conditions/comments min typ max unit digital inputs logic levels v il vio > 3 v ?0.3 +0.3 vio v vio 3 v ?0.3 +0.1 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial, 16 bits, twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.375 2.5 2.625 v vio specified per formance 2.3 5.5 v vio range functional range 1.8 5.5 v standby current 5, 6 vdd and vio = 2.5 v, t a = 25c 0.35 a ad7915 power dissipation vdd = 2.625 v, v ref = 5 v, vio = 3 v total 10 ksps throughput 70 w 1 msps thr oughput 7 9 mw vdd only 4 mw ref only 1.7 mw vio only 1.3 mw ad7916 power dissipation vdd = 2.625 v, v ref = 5 v, vio = 3 v total 500 ksps throughput 3.7 4.5 mw vdd only 2 mw ref only 0.85 mw vio only 0.85 mw energy per conversion 7.0 nj/ sam p le temperature range specified performance t min to t max ?40 +125 c 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 152.6 v. 2 see the terminology section. these specif ications include full temperature range variation but not the error contribution from the external reference. 3 all specifications expressed in decibels are referred to a full-scale input fsr and tested with an input signal at 0.5 db belo w full scale, unless otherwise specified. 4 dynamic range is obtained by oversamp ling the adc running at a throughput, f s , of 1 msps followed by postdigital filtering with an output word rate of f o . 5 with all digital inputs forced to vio or ground as required. 6 during acquisition phase.
data sheet ad7915/ad7916 rev. 0 | page 5 of 26 timing specifications t a = ?40c to +125c, vdd = 2.37 v to 2.63 v, vio = 2.3 v to 5.5 v, c load _ sdo = 20 pf, unless otherwise noted. see figure 2 for voltage levels. table 3. parameter symbol min typ max unit ad7915 throughput rate 1 msps conversion time: cnv rising edge to data available t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc 1 s ad7916 throughput rate 500 ksps conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v, x = 70 and y = 30. 2 minimum v ih and maximum v il used. see the digital inputs specifications in table 3. 12583-003 figure 2. voltage levels for timing
ad7915/ad7916 data sheet rev. 0 | page 6 of 26 absolute maximum ratings table 4. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to +3.0 v vdd to vio ?6 v to +3 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital output to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 10-lead msop 200c/w 10-lead lfcsp_wd 48.7c/w jc thermal impedance 10-lead msop 44c/w 10-lead lfcsp_wd 2.96c/w reflow soldering jedec standard (j-std-020) 1 see the analog inputs section for an explanation of in+ and in?. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet ad7915/ad7916 rev. 0 | page 7 of 26 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi/cs 9 sck 8 sdo 7 cnv 6 ad7915/ ad7916 top view (not to scale) 12583-004 figure 3. 10-lead ms op pin configuration notes 1. the exposed pad can be connected to gnd. this connection is not required to meet the electrical performances. 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi/cs 8sck 7sdo 6cnv ad7915/ ad7916 top view (not to scale) 12583-005 figure 4. 10-lead lfcsp pin configuration table 5. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is 2.4 v to 5.1 v. this pin is referred to the gnd pin and must be decoupled closely to the gnd pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di conversion input. this input has multiple functions. on its leading edge, cnv initiates the conversions and selects the interface mode of the device: chain mode or chip select (cs ) mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode , the data is read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the device is select ed, the conversion result is shifted out by this clock. 9 sdi/cs di serial data input/chip sele ct. this input has multiple functions. it selects the interface mode of the adc as follows: chain mode is selected if this pin is low du ring the cnv rising edge. in this mode, sdi/cs is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi/cs is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi/cs is high during the cnv rising edge. in this mode, either sdi/cs or cnv can enable the serial output signals when low. 10 vio p input/output interface digital power. this pin is nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). ep exposed pad. for the lead frame chip scale package (lfcsp), the exposed pad can be connected to gnd. this connection is not required to meet the electrical performances. 1 ai is analog input, p is power, di is digital input, and do is digital output.
ad7915/ad7916 data sheet rev. 0 | page 8 of 26 typical performance characteristics 0 65536 16384 32768 49152 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) code positive inl: +0.35 lsb negative inl: ?0.39 lsb 12583-405 figure 5. integral nonlinearity (inl) vs. code, ref = 5 v 0 65536 16384 32768 49152 positive inl: +0.39 lsb negative inl: ?0.44 lsb 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) code 12583-406 figure 6. inl vs. code, ref = 2.5 v 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 250 amplitude (db of full scale) frequency (khz) 12583-407 f s = 500ksps f in = 1khz snr = 94.98db thd = ?114.39db sfdr = ?114.73db sinad = 94.93db figure 7. ad7916 fft plot, ref = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 dnl (lsb) code 0 65536 16384 32768 49152 positive dnl: +0.31 lsb negative dnl: ?0.38 lsb 12583-408 figure 8. differential nonlinearity (dnl) vs. code, ref = 5 v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 dnl (lsb) code 0 65536 16384 32768 49152 positive dnl: +0.39 lsb negative dnl: ?0.39 lsb 12583-409 figure 9. dnl vs. code, ref = 2.5 v 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 250 amplitude (db of full scale) frequency (khz) 12583-410 f s = 500ksps f in = 1khz snr = 90.61db thd = ?117.23db sfdr = ?102.55db sinad = 90.61db figure 10. ad7916 fft plot, ref = 2.5 v
data sheet ad7915/ad7916 rev. 0 | page 9 of 26 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 amplitude (db of full scale) frequency (khz) 12583-500 f s = 1msps f in = 1khz snr = 95.06db thd = ?114.79db sfdr = ?116.64db sinad = 95.02db figure 11. ad7915 fft plot, ref = 5 v 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 ffe1 ffe2 ffe3 ffe4 ffe5 ffe6 ffe7 ffe8 ffe9 ffea number of occurrences codes in hex 12583-411 figure 12. histogram of a dc input at the code center, ref = 5 v 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 fff1 fff2 fff3 fff4 fff5 fff6 fff7 fff8 fff9 fffb fffa number of occurrences codes in hex 12583-414 figure 13. histogram of a dc input at the code center, ref = 2.5 v 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 200 300 400 500 amplitude (db of full scale) frequency (khz) 12583-501 f s = 1msps f in = 1khz snr = 91.21db thd = ?118.74db sfdr = ?108.7db sinad = 91.21db figure 14. ad7915 fft plot, ref = 2.5 v 40000 35000 30000 25000 20000 15000 10000 5000 0 ffd2 ffd3 ffd4 ffd5 ffd6 ffd7 ffd8 ffd9 ffda ffdb number of occurrences codes in hex 12583-412 figure 15. histogram of a dc input at the code transition, ref = 5 v 98 97 96 95 94 93 92 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 snr (db) input level (db) 12583-415 figure 16. snr vs. input level
ad7915/ad7916 data sheet rev. 0 | page 10 of 26 100 98 96 94 92 90 88 86 84 82 80 16.0 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 snr, sinad (db) enob (bits) reference voltage (v) snr sinad enob 12583-413 figure 17. snr, sinad, and enob vs. reference voltage 94.8 93.4 93.6 93.8 94.0 94.2 94.4 94.6 temperature (c) snr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 12583-418 figure 18. snr vs. temperature 96 85 86 87 88 89 90 91 92 93 94 95 10 input frequency (khz) sinad (db) 100 12583-417 figure 19. sinad vs. input frequency ? 95 ?125 ?110 ?115 ?105 ?100 ?120 115 85 100 95 105 110 90 2.25 5.25 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr 12583-416 figure 20. thd and sfdr vs. reference voltage ? 100 ?105 ?110 ?115 ?120 ?125 temperature (c) thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 12583-421 figure 21. thd vs. temperature ? 80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 10 input frequency (khz) thd (db) 100 12583-420 figure 22. thd vs. input frequency
data sheet ad7915/ad7916 rev. 0 | page 11 of 26 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 vdd voltage (v) i vdd i ref i vio operating currents (ma) 2.375 2.425 2.475 2.525 2.575 2.625 12583-118 figure 23. operating currents vs. vdd voltage ( ad7916 ) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 operating currents (ma) i vdd i ref i vio temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 12583-120 figure 24. operating currents vs. temperature ( ad7916 ) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 vdd voltage (v) i vdd i ref i vio operating currents (ma) 2.375 2.425 2.475 2.525 2.575 2.625 12583-121 figure 25. operating currents vs. vdd voltage ( ad7915 ) 8 7 6 5 4 3 2 1 0 power-down currents (a) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd + i vio 12583-303 figure 26. power-down currents vs. temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 operating currents (ma) i vdd i ref i vio temperature (c) ?55?35?155 25456585105125 12583-123 figure 27. operating currents vs. temperature ( ad7915 )
ad7915/ad7916 data sheet rev. 0 | page 12 of 26 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 29). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, and the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 00 to 100 01) occurs at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occurs for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. noise-free code resolution noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise-free code resolution = log 2 (2 n / peak-to-peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 db so that it includes all noise sources and dnl artifacts. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-noise-and-distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied.
data sheet ad7915/ad7916 rev. 0 | page 13 of 26 theory of operation comp control logic switches control busy output code cnv c c 2c 16,384c 4c 32,768c lsb sw+ msb lsb sw? msb c c 2c 16,384c 4c 32,768c in+ ref g nd in? 12583-020 figure 28. adc simplified schematic circuit information the ad7915 / ad7916 are high speed, low power, single-supply, precise, 16-bit adcs that use a successive approximation architecture. the ad7916 can convert 500,000 samples per second (500 ksps), whereas the ad7915 can convert 1,000,000 samples per second (1 msps); both devices power down between con- versions. when operating at 1 msps, the ad7915 typically consumes 7 mw, making the adc ideal for battery-powered applications. the ad7915 / ad7916 provide the user with an on-chip track- and-hold amplifier and do not exhibit any pipeline delay or latency, making these devices ideal for multiple multiplexed channel applications. the ad7915 / ad7916 can be interfaced to any 1.8 v to 5 v digital logic family. they are available in a 10-lead msop or a tiny 10-lead lfcsp that allows space savings and flexible configurations. converter operation the ad7915 / ad7916 are a successive approximation adcs based on a charge redistribution digital-to-analog converter (dac). figure 28 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /65,536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device returns to the acquisition phase, and the control logic generates the adc output code. because the ad7915/ ad7916 have an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
ad7915/ad7916 data sheet rev. 0 | page 14 of 26 transfer functions the ideal transfer characteristics for the ad7915 / ad7916 are shown in figure 29 and table 6. 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 12583-021 figure 29. adc ideal transfer function table 6. output codes and ideal input voltages description analog input v ref 5 v digital output code (he) +fsr C 1 lsb +4.999847 v 0x7fff 1 midscale + 1 lsb +152.6 v 0x00001 midscale 0 v 0x00000 midscale C 1 lsb ?152.6 v 0xffff Cfsr + 1 lsb ?4.999847 v 0x8001 Cfsr ?5 v 0x8000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection diagram figure 30 shows an example of the recommended connection diagram for the ad7915/ ad7916 when multiple supplies are available. 2.7nf 20 ? v? 0v to v ref v+ 4 2.7nf 20 ? v? v ref to 0v v+ 4 c ref 10f 2 ref 1 ref vdd vio gnd in+ in? sck sdo cnv ad7915/ ad7916 100nf 100nf 3-wire interface 2.5v 1.8v to 5.5v v+ ada4805-x 3 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see the recommended layout in figure 49 and figure 50. 3 see the driver amplifier choice section. 4 optional filter. see the analog inputs section. sdi/cs 12583-022 figure 30. typical application diagram with multiple supplies
data sheet ad7915/ad7916 rev. 0 | page 15 of 26 analog inputs figure 31 shows an equivalent circuit of the input structure of the ad7915 / ad7916. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v. if the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4805-1 or ada4805-2 , shown as ada4805-x in figure 30) are different from those of ref, the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. c pin ref r in c in d1 d2 in+ or in? gnd 12583-023 figure 31. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. 90 85 80 75 70 65 60 1k 10k 100k 1m 10m frequency (hz) cmrr (db) 12583-040 figure 32. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, when the switches are closed, the input impedance is limited to c pin . r in and c in make a one-pole, low- pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad7915/ ad7916 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the ad7915/ ad7916 are easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7915 / ad7916 . the noise from the driver is filtered by the one-pole, low-pass filter of the ad7915/ ad7916 analog input circuit made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7915/ ad7916 is 60 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 )( 2 60 60 log20 n 3db loss nef snr where: f C3db is the input bandwidth, in megahertz, of the ad7915/ ad7916 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, use a driver with a thd performance commensurate with the ad7915 / ad7916. ? for multichannel, multiplexed applications, the driver amplifier and the ad7915/ ad7916 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this settling may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. table 7. recommended driver amplifiers 1 amplifier typical application ada4805-1 / ada4805-2 very low noise, small, and low power ada4940-1 very low noise, low power, single to differential ada4941-1 very low noise, low power, single to differential ada4841-1 / ada4841-2 very low noise, small, and low power ada4897-2 very low noise and high frequency ad8655 5 v single supply, low noise ad8605, ad8615 5 v single supply, low power 1 for the latest recommended drivers, see the product recommendations listed on the ad7915/ ad7916 product webpage.
ad7915/ad7916 data sheet rev. 0 | page 16 of 26 20? 20? 10f r1 100nf +2.5v +5v ref +5.2v ?0.2v c f r2 r4 r6 10v, 5v, .. r3 r5 ref vdd gnd in+ in? ad7915/ ad7916 2.7nf 2.7nf ada4941-1 in fb out+ out? ref 100nf 12583-025 figure 33. single-ended to differential driver circuit single to differential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended to differential driver allows a differential input to the device. the schematic is shown in figure 33. the ada4940-1 , which is a fully differential amplifier, can be used as a single-ended to-differential driver as well. r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. make sure that the common mode is close to v ref /2. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. voltage reference input the ad7915 / ad7916 voltage reference input, ref, has a dynamic input impedance and must, therefore, be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031, ada4805-1 or the ad8605 ), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if a n u nbuffered refe rence voltage is used, th e decoupling value depends on th e reference used . for instance , a 22 f (x5r, 1206 size) ce ramic chip capacitor is appropriate for optimum performance using a low temperature drift adr433 reference. if desired, a reference decoupling capacitor with values as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7915/ ad7916 use two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together. the ad7915/ ad7916 are independent of power supply sequencing between vio and vdd. additionally, they are insensitive to power supply variations over a wide frequency range, as shown in figure 34. 95 90 85 80 75 70 65 60 psrr (db) 1k 10k 100k 1m frequency (hz) 12583-139 figure 34. power supply rejectio n ratio (psrr) vs. frequency the ad7915 / ad7916 power down automatically at the end of each conversion phase. digital interface although the ad7915/ ad7916 have a reduced number of pins, they offer flexibility in their serial interface modes. when in cs mode, the ad7915/ ad7916 are compatible with spi, qspi?, mircrowire?, digital hosts, and dsps. in this mode, the ad7915 / ad7916 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections, which is useful, for instance, in isolated applications. a 4-wire interface using the sdi/ cs , cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi).
data sheet ad7915/ad7916 rev. 0 | page 17 of 26 this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7915 / ad7916 provide a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line, similar to a shift register. the mode in which the device operates depends on the sdi/ cs level when the cnv rising edge occurs. cs mode is selected if sdi/ cs is high, and chain mode is selected if sdi/ cs is low. the sdi/ cs hold time is such that when sdi/ cs and cnv are connected together, chain mode is always selected. in either mode, the ad7915 / ad7916 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and to trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled ? in cs mode if cnv or sdi is low when the adc conversion ends (see figure 38 and figure 42). ? in chain mode if sck is high during the cnv rising edge (see figure 46). cs mode, 3-wire, without busy indicator this mode is usually used when a single ad7915 / ad7916 is connected to an spi-compatible digital host. the connection diagram is shown in figure 35, and the corresponding timing is given in figure 36. with sdi/ cs tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. when the conversion is complete, the ad7915 / ad7916 enter the acquisition phase and power down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad7915/ ad7916 sdo cnv sck convert data in clk digital host vio sdi/cs 12583-027 figure 35. cs mode without busy indicator, 3-wire connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 1 2 3 14 15 16 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition t acq t en sdi/cs = 1 12583-028 figure 36. cs mode without busy indicator, 3-wire serial interface timing (sdi high)
ad7915/ad7916 data sheet rev. 0 | page 18 of 26 cs mode 3-wire, with busy indicator this mode is typically used when a single ad7915 / ad7916 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 37, and the corresponding timing is given in figure 38. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7915/ ad7916 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17 th sck falling edge, or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad7915 / ad7916 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. ad7915/ ad7916 sdo sdi data in irq digital host convert clk vio vio 47k ? cnv sck 12583-017 figure 37. 3-wire cs mode with busy indi cator connection diagram (sdi high) t conv t cnvh t cyc aquisition aquisition t acq t sck t sckh t sckl conversion sck cnv sdi = 1 sdo d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis 12583-018 figure 38. 3-wire cs mode with busy indi cator serial interface timing (sdi high)
data sheet ad7915/ad7916 rev. 0 | page 19 of 26 cs mode, 4-wire, without busy indicator this mode is usually used when multiple ad7915 / ad7916 devices are connected to an spi-compatible digital host. a connection diagram example using two ad7915 / ad7916 devices is shown in figure 39, and the corresponding timing is given in figure 40. with sdi high, a rising edge on cnv initiates a conversion, selects sdi/ cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data read back; if sdi/ cs and cnv are low, sdo is driven low. prior to the minimum conversion time, sdi/ cs can be used to select other spi devices, such as analog multiplexers, but sdi/ cs must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. when the conversion is complete, the ad7915/ ad7916 enter the acquisition phase and power down. each adc result can be read by bringing its sdi/ cs input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge ca n be used t o ca pture th e d ata, a d igital host using the sck falling edge al lows a faster reading rate, provided tha t i t has an acceptable hold time . after the 16 th sck falling edge o r w he n sdi/ cs goes high (whiche ver occurs first), sdo returns to high impedance and another ad7915/ad7916 c an be read. ad7915/ ad7916 sdo cnv sck convert data in clk digital host cs1 cs2 ad7915/ ad7916 sdo cnv sck sdi/cs sdi/cs 12583-029 figure 39. cs mode without busy indicator, 4-wire connection diagram sdo d15 d14 d13 d1 d0 t dis sck 123 30 3132 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d15 d14 17 18 16 sdi/cs (cs1) sdi/cs (cs2) 12583-030 figure 40. cs mode without busy indicator, 4-wire serial interface timing
ad7915/ad7916 data sheet rev. 0 | page 20 of 26 cs mode 4-wire with busy indicator this mode is usually used when a single ad7915 / ad7916 is connected to an spi-compatible digital host that has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 41, and the corresponding timing is given in figure 42. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7915 / ad7916 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or sdi going high, whichever is earlier, the sdo returns to high impedance. ad7915/ ad7916 sdo sdi data in irq digital host convert cs1 clk vio 47k ? cnv sck 12583-300 figure 41. 4-wire cs mode with busy indi cator connection diagram t cyc t conv t ssdicnv t hsdicnv t en t hsdo t dsdo t sckh t sckl t sck t dis aquisition aquisition t acq conversion sdi sck cnv s d o d15 d14 d1 d0 123 15 1617 12583-301 figure 42. 4-wire cs mode with busy indicator serial interface timing
data sheet ad7915/ad7916 rev. 0 | page 21 of 26 chain mode, without busy indicator this mode can be used to daisy-chain multiple ad7915/ ad7916 devices on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7915 / ad7916 devices is shown in figure 43, and the corresponding timing is given in figure 44. when sdi/ cs and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, and selects the chain mode. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7915/ ad7916 enter the acquisition phase and power down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7915/ ad7916 devices in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. convert data in clk digital host ad7915/ ad7916 sdo cnv b sck ad7915/ ad7916 sdo cnv a sck sdi/cs sdi/cs 12583-031 figure 43. chain mode without busy indicator connection diagram d a 15 d a 14 d a 13 sck 123 30 3132 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdo b d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 sdi/cs a = 0 sdo a = sdi/cs b 12583-032 figure 44. chain mode without busy indicator serial interface timing
ad7915/ad7916 data sheet rev. 0 | page 22 of 26 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7915 / ad7916 devices on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multi- converter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7915/ ad7916 devices is shown in figure 45, and the corresponding timing is given in figure 46. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7915 / ad7916 adc labeled c in figure 45) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7915/ ad7916 then enter the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7915/ ad7916 devices in the chain, provided that the digital host has an acceptable hold time. ad7915/ ad7916 c sdo sdi data in irq digital host convert clk cnv sck ad7915/ ad7916 b sdo sdi cnv sck ad7915/ ad7916 a sdo sdi cnv sck 12583-302 figure 45. chain mode with bu sy indicator connection diagram t conv t cyc t ssdisck t sckh t sck t hsdisc t acq t dsdosdi t dsdosdi t dsdodsi aquisition t ssdicnv aquisition t sckl conversion t hsdicnv sck cnv = sdi a sdo a = sdi b sdo b = sdi c sdo c t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d c 15 d c 14 d c 13 d b 1d b 0d a 15 d a 14 d a 1d a 0 d c 1d c 0d b 15 d b 14 d a 0 d a 1 d b 0 d b 1d a 14 d a 15 d a 1d a 0 t hsdo 123 151617 4 1819 3132333435 474849 t dsdo t dsdosdi t dsdosdi 12583-026 figure 46. chain mode with busy indicator serial interface timing
data sheet ad7915/ad7916 rev. 0 | page 23 of 26 applications information interfacing to blackfin dsp the ad7915 / ad7916 can easily connect to a blackfin? dsp spi or sport. the spi configuration is straightforward using the standard spi interface, as shown in figure 47. ad7915/ ad7916 sck sdo cnv spi_clk spi_miso spi_mosi dsp 12583-035 figure 47. typical connection to blackfin spi interface similarly, the sport interface can be used to interface to this adc. the sport interface has some benefits in that it can use direct memory access (dma) and provides a lower jitter cnv signal generated from a hardware counter. some glue logic may be required between sport and the ad7915/ ad7916 interface. the evaluation board for the ad7915/ ad7916 interfaces directly to the sport of the blackfin-based ( adsp-bf527 ) sdp board. the configuration used for the sport interface requires the addition of some glue logic as shown in figure 48. the sck input to the adc was gated off when cnv was high to keep the sck line static while converting the data, thereby ensuring the best integrity of the result. this approach uses an and gate and a not gate for the sck path. the other logic gates used on the rsclk and rfs paths are for delay matching purposes and may not be necessary when path lengths are short. this is one approach to using the sport interface for this adc; there may be other solutions similar to this approach. layout design the printed circuit board that houses the ad7915/ ad7916 so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7915/ ad7916 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7915/ ad7916 is used as a shield. do not run fast switching signals, such as cnv or clocks, near analog signal paths. avoid crossover of digital and analog signals. using at least one ground plane is recommended. it can be common or split between the digital and analog sections. in the latter case, join the planes underneath the ad7915 / ad7916 devices. the ad7915 / ad7916 voltage reference input, ref, has a dynamic input impedance. decouple ref with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to, but ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, decouple the power supplies of the ad7915 / ad7916, vdd and vio, with ceramic capacitors, typically 100 nf, placed close to the ad7915/ ad7916 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 49 and figure 50. sck sdo cnv tsclk dr tfs rfs rsclk v drive ad7915/ ad7916 dsp 12583-045 figure 48. evaluation board connect ion to blackfin sport interface
ad7915/ad7916 data sheet rev. 0 | page 24 of 26 evaluating ad7915/ ad7916 performance other recommended layouts for the ad7915/ ad7916 are outlined in ug-340 , the user guide of the evaluation board for the ad7915/ ad7916 ( eval-ad7915sdz / eval-ad7916sdz ). the evaluation board package includes a fully assembled and tested evaluation board, the user guide, and software for controlling the board from a pc via the eval-sdp-cb1z . ad7915/ ad7916 12583-033 figure 49. recommended layout of the ad7915 / ad7916 (top layer) 12583-034 figure 50. recommended layout of the ad7915 / ad7916 (bottom layer)
data sheet ad7915/ad7916 rev. 0 | page 25 of 26 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 51. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0 2-05-2013-c top view bottom view 0.20 min figure 52. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1, 2, 3 temperature range package description package option ordering quantity branding AD7915BRMZ ?40c to +125c 10-lead msop, tube rm-10 50 c85 AD7915BRMZ-rl7 ?40c to +125c 10-lead ms op, 7 tape and reel rm-10 1,000 c85 ad7915bcpz-rl7 ?40c to +125c 10-lead lfcsp_ wd, 7 tape and reel cp-10-9 1,500 c87 ad7916brmz ?40c to +125c 10-lead msop, tube rm-10 50 c86 ad7916brmz-rl7 ?40c to +125c 10-lead ms op, 7 tape and reel rm-10 1,000 c86 ad7916bcpz-rl7 ?40c to +125c 10-lead lfcsp_ wd, 7 tape and reel cp-10-9 1,500 c87 eval-ad7915sdz evaluation board eval-ad7916sdz evaluation board eval-sdp-cb1z system demonstrat ion board, used as a controller board for data transfer via a usb interface to pc 1 z = rohs compliant part. 2 the eval-ad7915dz and eval-ad7916sdz boards can be used as standalone evaluation boards, or in conjunction with the eval-sdp-cb1z for evaluation and demonstration purposes. 3 the eval-sdp-cb1z board allows a pc to contr ol and communicate with all analog devices, inc., evaluation boards ending in the sd designator.
ad7915/ad7916 data sheet rev. 0 | page 26 of 26 notes ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12583-0-3/15(0)

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